1. Field of the Invention
The present invention generally relates to central processing units, and more particularly to a central processing unit which has an inhibited area which is not allowed to become a branch destination, and the operation of the central processing unit is immediately shifted to an exception process when the operation is attempted to branch to the inhibited area.
2. Background of the Invention
A central processing unit (hereinafter simply referred to as a CPU) sequentially reads and executes instructions from a memory device in which a group of instructions are stored as a program. Hereinafter, such as memory device is simply referred to as a memory.
Generally, data equal to one byte consisting of eight bits is assigned one address. When the CPU has a 16-bit data bus serving as a data transmission path, data or an instruction equal to two bytes can be accessed at one time. At this time, the CPU specifies two addresses to the memory. However, generally the CPU is equipped with a single address bus used to specify the address. Hence, the single address bus is used so that two consecutive addresses equal to two types in total are specified in such a way that one of the two consecutive addresses has the least significant bit of "0" and the other address has the least significant bit of "1". The other bits of the two consecutive addresses are the same as each other. Hence, two bytes to be accessed are two consecutive bytes starting from an even address, and the address specified by the CPU is such an even address.
When two bytes starting from an odd address should be accessed, the odd address and the subsequent even address cannot be simultaneously accessed. That is, the access must be carried out twice. This reduces the time-efficiency. When taking into consideration the above matters, it is preferable, in view of efficiently, that data or an instruction equal to two bytes should be arranged so as to be accessed by an even address.
There is an improved CPU having a restriction such that instructions of a program are always arranged at even addresses in order to simultaneously read an instruction of two bytes when the instruction code length of the CPU having a data bus having a 16-bit width is equal to 16 bits. Such a CPU having the above restriction is, for example, CPU68000 manufactured by Motolora Inc. Generally, the above restriction is called an even alignment restriction and is widely employed in various CPUs.
The CPU having the even alignment restriction always reads the instruction from an even address. Hence, the program counter indicating the address of the instruction to be executed is always an even number. If the program counter is updated due to, for example, execution of a branch instruction and the updated counter value is an odd number, the CPU executes, as an exception process, a process for branching to an exception process routine. Since the above exception process is performed when the program counter is attempted to be updated with the odd address, it is always necessary to determine whether the updated value is an even number or an odd number when updating the program counter.
It is necessary to describe a microprogram controlling the operation of the CPU so that, in all cases where the program counter is updated, it is determined whether or not the updated counter value is an odd number, and that the CPU operation branches to the exception process routine in the microprogram when it is determined that the updated counter value is an odd number and the CPU operation shifts to a next process when it is determined that the updated counter value is an even number.
Another type of CPUs is known in which the whole address space accessible by the CPU is equally divided into two parts on the basis of whether the most significant bit of the address is "1" or "0". Further, there is provided a restriction such that some operation modes among a plurality of predetermined operation modes are not allowed to jump to one of the two half address spaces. If jumping to the jump-inhibited half address space is attempted under the above restriction, an exception process takes place. Hence, when updating the program counter in execution of an instruction in the jump-inhibited operation mode, it is necessary to refer to the most significant bit of the updated counter value and determine whether or not the most significant bit indicates the jump-allowed half address space.
Hence, it is necessary to describe a microprogram controlling the operation of the CPU so that, in all cases where the program counter is updated, it is determined whether or not the updated counter value indicates the jump-allowed half address space, and that the CPU operation branches to the exception process routine in the microprogram when it is determined that the updated counter value indicates the jump-inhibited half address space, and the CPU operation shifts to a next process when it is determined that the updated counter value indicates the jump-allowed half address space.
There is also known a CPU which is an improvement in the above CPU having the restriction regarding the two half address spaces. Such a CPU has a register in which an arbitrary value can be written and is always compared with the content of the program counter. When the comparison result does not meet (or meets) the predetermined condition, an exception process is carried out. In the other cases, the CPU executes the ordinary operation.
Even in the above case, it is necessary to describe a microprogram controlling the operation of the CPU so that, in all cases where the program counter is updated, it is determined whether or not the comparison results meets the predetermined condition, and that the CPU operation branches to the exception process routine in the microprogram when it is determined that the comparison result does not meet (or meets) the predetermined condition, and the CPU operation shifts to a next step when it is determined that the comparison result meets (or does not meet) the predetermined condition.
The CPU described just above will now be described with reference to FIG. 1, which shows the structure of the above CPU. The CPU shown in FIG. 1 is made up of a decoder (DEC) 1, an execution unit (also referred to as a data path: DP) 2, an instruction register (IR) 3 and a timing control unit (TCU) 4. The decoder 1 is the main control part of the CPU and has input terminals connected to the output terminals of the instruction register 3 and the timing control unit 4. The output terminals of the decoder 1 are connected to the input terminals of the execution unit 2, the instruction register 3 and the timing control unit 4. The execution unit 2 executes operations on data and temporarily stores data.
The decoder 1 is supplied with information of an instruction code from the instruction register 3 and information of the execution step from the timing control unit 4. Then, the decoder 1 refers to a microprogram provided therein, and sends control signals 101 to the execution unit 2, a control signal 102 to the instruction register 2 and a control signal 103 to the timing control unit 4.
The execution unit 2 includes a program counter. When an odd program counter value is set in the program counter, the execution unit 2 informs the decoder 1 of the above set by means of a monitor signal 201. The instruction register 3 stores instruction codes, which are sent to the decoder 1 via signal lines 301. The instruction register 3 is updated to the next instruction code in response to the instruction by the control signal 102. The updating to the next instruction code is carried out when execution of the current instruction code is completed. The decoder 1 notifies the instruction register 3 of the above updating timing by means of the control signal 102.
The timing control unit 4 controls the execution step of the instruction. The decoder 1 is notified of the execution step by means of timing signals 401. The timing control unit 4 sets the first execution step of an instruction to "0" and then performs the sequential counting operation. However, the timing control unit 4 is capable of generating an arbitrary counter value for reasons of the microprogram. The timing control unit 4 is notified of the setting to an arbitrary counter value by means of the control signal 103 produced by the decoder 1. When execution of the current instruction is completed, the execution step specified by the timing control unit 4 is set to "0".
FIG. 2 is a timing chart of the operation of the CPU shown in FIG. 1. It will now be assumed that there is a description in the microprogram such that, at an operation timing [11] shown in part (a) of FIG. 2, the address of a jump destination is stored to the program counter provided in the execution unit 2 via an internal data bus provided therein used to transmit data. The decoder 1 performs the decoding operation at the operation timing [11] in part (a) of FIG. 2, and outputs the decoder output at timing [21] of the decoder output signal shown in part (b) thereof. Hereinafter, the decoder output signal produced in the above-mentioned way is referred to as a control signal DB.sub.-- PC. According to the control signal DB.sub.-- PC at the timing [21], the execution unit 2 fetches the address of the jump destination available on the internal data bus provided therein. Then, the execution unit 2 notifies, by means of the control signal 201, the decoder of whether the address of the jump destination is an odd address or an even address. The decoder 1 receives the above notification, and selects a process in which the microprogram completes the instruction due to the normal jumping operation or another process in which the microprogram executes the exception process due to occurrence of the odd address.
There are two microprogram parts to be executed at the operation timing [13], one of the parts being executed upon the normal completion, and the other part being executed upon the exception occurrence. This is because information output by the executing unit 2 at the timing [31] can be processed by the decoding process executed at the timing [13]. In the normal completion, the decoder 1 instructs the instruction register 3 to update the instruction to the next one at the operation timing [13], and instructs the timing control unit 4 to set the counter value to "0". In the above way, decoding of the next instruction can be started at the timing [14] in the normal completion. Hence, the operation to be executed in the normal completion is carried out at the operation timing [13]. Hence, the fastest process is such that the control signal DB.sub.-- PC is decoded at the timing [11] and the next instruction is processed at the timing [14].
As described above, it is determined whether the updated counter value is an odd number or even number each time the program counter is updated. That is, even when the updated counter value is an even number, the microprogram needs the steps of making the above decision. Hence, it takes a long time to execute the program. Further, the microprogram has a large load, which leads an increase in the size of the microprogram.
The CPU which determines whether the jump-allowed half address space is accessed has a disadvantage in that the microprogram provided therein needs the steps of making the above decision even when the jump-allowed half address space is accessed. Hence, it takes a long time to execute the program. Further, the microprogram has a large load, which leads an increase in the size of the microprogram.
The CPU which determines whether the comparison result meets (or does not meet) the predetermined condition has a disadvantage in that the microprogram provided therein needs the steps of making the above decision even when the comparison results meets (or does not meet) the predetermined condition. Hence, it takes a long time to execute the program. Further, the microprogram has a large load, which leads an increase in the size of the microprogram.